Según la pregunta vinculada, la solución más simple es hacer que el procesador clásico realice tales operaciones si es posible . Por supuesto, eso puede no ser posible, por lo que queremos crear un sumador .
Hay dos tipos de sumadores de un solo bit: el sumador y el sumador completo . El medio sumador toma las entradas y B y emite la 'suma' (operación XOR) S = A ⊕ B y el 'carry' (operación Y) C = A ⋅ B . Un sumador completo también tiene la 'acarreo en' C i n de entrada y el 'llevar a cabo' de salida C o u t , sustituyendo C . Esto devuelve S = A C o u t = CUNAsiS= A ⊕ Bdo= A ⋅ Bdoyo ndoo u tdoS= A ⊕ B ⊕ Cyo n y .doo u t= Cyo n⋅ ( A + B ) + A ⋅ B
Versión cuántica del medio sumador
Mirando la puerta CNOT en el registro de qubit registro de control B : CNOT A → B | 0 ⟩ A | 0 ⟩ BUNAsi
CNOTA→B|0⟩A|0⟩BCNOTA→B|0⟩A|1⟩BCNOTA→B|1⟩A|0⟩BCNOTA→B|1⟩A|1⟩B=|0⟩A|0⟩B=|0⟩A|1⟩B=|1⟩A|1⟩B=|1⟩A|0⟩B,
which immediately gives the output of the
B register as
A⊕B=S. However, we have yet to compute the carry and the state of the
B register has changed so we also need to perform the AND operation. This can be done using the 3-qubit Toffoli (controlled-CNOT/CCNOT) gate. This can be done using registers
A and
B as control registers and initialising the third register
(C) in state
|0⟩, giving the output of the third register as
A⋅B=C. Implementing Toffoli on registers
A and
B controlling register
C followed by CNOT with
A controlling
B gives the output of register
B as the sum and the output of register
C as the carry. A quantum circuit diagram of the half-adder is shown in figure 1.
Figure 1: Circuit Diagram of a half-adder, consisting of Toffoli followed by CNOT. Input bits are A and B, giving the sum S with carry out C.
Quantum version of the full adder
Shown in figure 2, a simple way of doing this for single bits is by using 4 qubit registers, here labelled A, B, Cin and 1, where 1 starts in state |0⟩, so the initial state is |A⟩|B⟩|Cin⟩|0⟩:
- Apply Toffoli using A and B to control 1: |A⟩|B⟩|Cin⟩|A⋅B⟩
- CNOT with A controlling B: |A⟩|A⊕B⟩|Cin⟩|A⋅B⟩
- Toffoli with B and Cin controlling 1: |A⟩|A⊕B⟩|Cin⟩|A⋅B⊕(A⊕B)⋅Cin=Cout⟩
- CNOT with B controlling Cin: |A⟩|A⊕B⟩|A⊕B⊕Cin=S⟩|Cout⟩
A final step to get back the inputs A and B is to apply a CNOT with register A controlling register B, giving the final output state as
|ψout⟩=|A⟩|B⟩|S⟩|Cout⟩
This gives the output of register Cin as the sum and the output of register 2 as carry out.
Figure 2: Circuit diagram of a full adder. Input bits are A and B along with a carry in Cin, giving the sum S with carry out Cout.
Quantum version of the ripple carry adder
A simple extension of the full adder is a ripple carry adder, named as it 'ripples' the carry out to become the carry in of the next adder in a series of adders, allowing for arbitrarily-sized (if slow) sums. A quantum version of such an adder can be found e.g. here
Actual implementation of a half-adder
For many systems, implementing a Toffoli gate is far from as simple as implementing a single qubit (or even two qubit) gate. This answer gives a way of decomposing Toffoli into multiple smaller gates. However, in real systems, such as IBMQX, there can also be issues on which qubits can be used as targets. As such, a real life implementation on IBMQX2 looks like this:
Figure 3: Implementation of a half-adder on IBMQX2. In addition to decomposing the Toffoli gate into multiple smaller gates, additional gates are required as not all qubit registers can be used as targets. Registers q[0] and q[1] are added to get the sum in q[1] and the carry in q[2]. In this case, the result q[2]q[1] should be 10. Running this on the processor gave the correct result with a probability of 42.8% (although it was still the most likely outcome).
``If I was using diodes, transistors etc I could easily figure out myself the classical operations I need to run to add 1+1. How would you do that, in detail, on a quantum computer?''
Impressive! I suspect that most people cannot easily figure out themselves how to combine diodes and transistors to implement a classical two-bit adde (though I do not doubt this material scientist can probably do it). ;)
Theoretically, the way you implement a classical adder is pretty similar in a classical and quantum computer: you can do that in both cases by implementing a Toffoli gate! (See @Mithrandir24601's answer.)
But the material scientist probably wants to understand how to implement such an gate (or an equivalence sequence of other quantum gates) on a physical device. There are probably an infinite ways to do that using different quantum technologies, but here are two direct realizations of this gate using trapped ions and superconducting qubits:
You can also decompose the Toffoli gate as a sequence of single-qubit and CNOT gates. https://media.nature.com/lw926/nature-assets/srep/2016/160802/srep30600/images/srep30600-f5.jpg
You can read about how to implement these with photonics, cavity-QED and trapped ions in Nielsen and Chuang.
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A new method for computing sums on a quantum computer is introduced. This technique uses the quantum Fourier transform and reduces the number of qubits necessary for addition by removing the need for temporary carry bits.
PDF link for 'addition on a quantum computer', written by Thomas G. Draper, written September 1, 1998, revised: June 15, 2000.
To summarize the above link, addition is performed according to the following circuit diagram (taken from page 6):
To quote the paper (again, page 6):
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Parallel computation of the sum of two qubits
I wanted to experience parallel computation of the sum of two qubits, a superposition of 0 and "1 with phase -1" added to 1; and I was inspired by Mithrandir24601's answer. The results are below. I hope my answer is within the context of what was asked. It shows how 1 is added 1, and to 0, at the same time, but whilst both answers are calculated, we can read out the answer to only one of the calculations each time the computation is run. You can see that out of 1000 runs, 417 times we read out the answer "1" (1=0+1), and 380 times and we read out the answer "2" (2=1+1).
(34 times we got nought when the 1 bit was flipped to nought, 54 times we got 0=0+1, 29 times we got 1=1+1, 28 times we got 2=0+1, 42 times we got 3=0+1, and 16 times we got 3=1+1; each of these errors arising no doubt from bit flips, phase flips, or both).
I thought an initialπ phase (created in the 1st of 3 Hadamard gates) represented a negative digit, but it just represents a positive digit with a -1 phase factor.
A superposition of 0 and "1 with phase -1" in a one qubit register is added to 1 in a two-qubit register. With three qubits, the first two qubits left to right is the sum (or the 3rd and 4th of 5) and the right-most qubit shows whether the ground state (treated as 0) was added or the excited state (1 with an initial phase of -1) was added.
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